Fault–tolerant architecture for serial–parallel multipliers

IF 0.6 Q4 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS

INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY Pub Date : 2014-08-04 DOI:10.1504/IJCAT.1998.062190

A. A. El-Gawad

引用次数: 0

Abstract

An efficient fault–tolerant architecture for use in serial–parallel multipliers is proposed. This architecture uses a time redundancy method together with the technique of a fast serial–parallel multiplier to achieve both error detection and error location with small time and hardware overheads. The design is most suitable for use in VLSI circuits and digital signal processing applications where serial data is available.

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串并联乘法器的容错架构

提出了一种适用于串并联乘法器的高效容错结构。该体系结构采用时间冗余方法和快速串并联乘法器技术，以较小的时间和硬件开销实现错误检测和错误定位。该设计最适合用于具有串行数据的VLSI电路和数字信号处理应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS-

CiteScore

2.80

自引率

45.50%

发文量

期刊介绍： IJCAT addresses issues of computer applications, information and communication systems, software engineering and management, CAD/CAM/CAE, numerical analysis and simulations, finite element methods and analyses, robotics, computer applications in multimedia and new technologies, computer aided learning and training. Topics covered include: -Computer applications in engineering and technology- Computer control system design- CAD/CAM, CAE, CIM and robotics- Computer applications in knowledge-based and expert systems- Computer applications in information technology and communication- Computer-integrated material processing (CIMP)- Computer-aided learning (CAL)- Computer modelling and simulation- Synthetic approach for engineering- Man-machine interface- Software engineering and management- Management techniques and methods- Human computer interaction- Real-time systems