{"title":"Increasing the Fault Coverage of a Truncated Test Set","authors":"I. Pomeranz","doi":"10.1145/3508459","DOIUrl":null,"url":null,"abstract":"Defect-aware, cell-aware, and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an \\( n \\) -input subcircuit can have up to \\( 2^n \\) faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by \\( T_1 \\) obtained after truncating a larger test set denoted by \\( T_0 \\) . Suppose that the truncation reduces the set of detected faults from the set denoted by \\( D_0 \\) to the set denoted by \\( D_1 \\) . The procedure described in this article modifies the tests in \\( T_1 \\) to gain the detection of faults from \\( D_0 \\) \\( \\setminus \\) \\( D_1 \\) , even at the cost of losing the detection of faults from \\( D_1 \\) . The goal is to reduce the fault coverage loss by computing a test set denoted by \\( T_2 \\) that detects a set of faults denoted by \\( D_2 \\) such that \\( |T_2| = |T_1| \\) and \\( |D_2| \\gt |D_1| \\) . Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.","PeriodicalId":6933,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","volume":"80 1","pages":"1 - 16"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Transactions on Design Automation of Electronic Systems (TODAES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3508459","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Defect-aware, cell-aware, and gate-exhaustive faults are described by input patterns of subcircuits or cells that are expected to activate defects. Even with single-cycle faults, an \( n \) -input subcircuit can have up to \( 2^n \) faults with unique fault detection conditions, resulting in a large test set. Such a test set may have to be truncated to fit in the tester memory or satisfy constraints on test application time. In this case, a loss of fault coverage is inevitable. This article considers the test set denoted by \( T_1 \) obtained after truncating a larger test set denoted by \( T_0 \) . Suppose that the truncation reduces the set of detected faults from the set denoted by \( D_0 \) to the set denoted by \( D_1 \) . The procedure described in this article modifies the tests in \( T_1 \) to gain the detection of faults from \( D_0 \) \( \setminus \) \( D_1 \) , even at the cost of losing the detection of faults from \( D_1 \) . The goal is to reduce the fault coverage loss by computing a test set denoted by \( T_2 \) that detects a set of faults denoted by \( D_2 \) such that \( |T_2| = |T_1| \) and \( |D_2| \gt |D_1| \) . Experimental results for benchmark circuits demonstrate the ability of the procedure to increase the coverage of gate-exhaustive faults over several iterations.