An FPGA-based transient error simulator for evaluating resilient system designs (abstract only)

Abstract

Error-resilient designs have become more important with the continued device scaling. One critical challenge of designing error-resilient systems is the lack of tools to quickly and accurately evaluate the effectiveness and performance of such systems. We propose an FPGA-based transient error simulator to accelerate transient error simulations incorporating accurate datapath delay models and realistic error models. Compared to conventional digital error simulators, the FPGA-based transient error simulator operates at a finer time step and captures intricate interactions between errors and datapath under different circuit-level error detection and correction techniques. The error simulator is constructed using configurable datapath delay model and error model, making it general-purpose and widely applicable. We demonstrate the capability of this simulator in the evaluation of two popular error-resilient design techniques, pre-edge and post-edge detection and correction, using a synthesized CORDIC processor and an Alpha processor that operate under soft error, coupling noise and voltage droop models. The proposed error simulator uncovers insights to guide practical designs, including the choice of checking window in pre-edge designs and the optimal operating frequency in post-edge designs. The FPGA-based transient simulation will complement circuit simulation and system emulation for resilient system designs.