A 13-bit Hybrid Interpolated SAR ADC

Abstract

In order to adapt to the application of electronic devices such as wideband receivers, high-precision and high-speed ADCs have become a hot research topic. In this paper, a 13-bit successive approximation analog-to-digital converter (SAR ADC) with a conversion rate of 500-MS/s is introduced. The voltage domain interpolation (Interpolated) technique is used to achieve 4 bits per conversion, and the number of reduced comparators is reduced to half by using the time domain interpolation structure. The SAR ADC redundancy correction technique based on the pipelined ADC redundancy correction principle is investigated and discussed, allowing the ADC to have ± 0.5 LSB misalignment per conversion.