Fast and accurate back propagation method for reliability evaluation of logic circuits

2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) Pub Date : 2018-01-01 DOI:10.1109/EICONRUS.2018.8317364

A. Stempkovskiy, D. Telpukhov, V. Nadolenko

{"title":"Fast and accurate back propagation method for reliability evaluation of logic circuits","authors":"A. Stempkovskiy, D. Telpukhov, V. Nadolenko","doi":"10.1109/EICONRUS.2018.8317364","DOIUrl":null,"url":null,"abstract":"Paper presents an enhanced method for computation of logic gates' observabilities at circuit outputs, which are used as technology-independent metric for circuit reliability. When bit-parallel simulation is being applied, circuit's ability to propagate errors from each certain gate to its outputs is presented as set of ODC (observability-don't-care) masks. Proposed method for calculating ODCs is based on both direct error simulation and back propagation, being accurate as former in presence of reconvergent branches and almost as fast as latter in their absence. In addition, reconvergence handling is further improved by implementation of reduced circuit structure. Proposed algorithm has been applied to ISCAS85 benchmark circuits and then compared to error simulation and back propagation algorithms. Thus it is proven to provide accurate ODCs for given sequence of input sets being considerably faster than complete simulation. Results of computational experiments are also present in paper.","PeriodicalId":6562,"journal":{"name":"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","volume":"5 1","pages":"1424-1429"},"PeriodicalIF":0.0000,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EICONRUS.2018.8317364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

Abstract

Paper presents an enhanced method for computation of logic gates' observabilities at circuit outputs, which are used as technology-independent metric for circuit reliability. When bit-parallel simulation is being applied, circuit's ability to propagate errors from each certain gate to its outputs is presented as set of ODC (observability-don't-care) masks. Proposed method for calculating ODCs is based on both direct error simulation and back propagation, being accurate as former in presence of reconvergent branches and almost as fast as latter in their absence. In addition, reconvergence handling is further improved by implementation of reduced circuit structure. Proposed algorithm has been applied to ISCAS85 benchmark circuits and then compared to error simulation and back propagation algorithms. Thus it is proven to provide accurate ODCs for given sequence of input sets being considerably faster than complete simulation. Results of computational experiments are also present in paper.

查看原文本刊更多论文

逻辑电路可靠性评估的快速准确反向传播方法

本文提出了一种计算电路输出处逻辑门可观测性的改进方法，并将其作为电路可靠性的技术无关度量。当应用位并行仿真时，电路将错误从每个特定门传播到其输出的能力表现为一组ODC(可观察性-不在乎)掩码。本文提出的odc计算方法基于直接误差模拟和反向传播，在存在再收敛分支时与前者一样准确，而在不存在再收敛分支时几乎与后者一样快。此外，通过简化电路结构的实现，进一步改善了再收敛处理。将该算法应用于ISCAS85基准电路，并与误差仿真和反向传播算法进行了比较。因此，它被证明为给定的输入集序列提供准确的odc，比完全模拟要快得多。文中还给出了计算实验结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)

自引率

0.00%

发文量