Design of 850 GHz 2×2 Array Heterodyne-receiver Chips Based on Schottky-diode GaAs Process

Abstract

This paper introduces the design and implementation of array heterodyne-receiver chips working at 850GHz. For the designing process of high-integrated array chips, the parasitic effect is one of the major difficulties. To reduce the influence of parasitic effect, the mixer is designed to utilize a parallel diode which simplifies the direct-current bias circuit, LO is designed to adopt a direct nine-fold multiplier chain. As a result, array monolithic chips in symmetrical $2 \times2$ form have high integration and low noise figure. The simulation results prove the rationality, correctness, and feasibility of the design, which has reference significance for the engineering research of terahertz domain.