A new CMOS compatible high performance first-order all-pass filter realisation

Q3 Engineering
B. Chaturvedi, J. Mohan, Shiv Narain Gupta
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引用次数: 2

Abstract

ABSTRACT A new realisation of an electronically tunable first-order voltage-mode all-pass filter enjoying the feature of low voltage and low power is proposed in this paper. The proposed realisation of filter employs only one active element namely differential voltage extra-x current controlled conveyor and one grounded capacitor. The use of minimal number of components makes the proposed structure simple and attractive from chip fabrication point of view. The performance of proposed structure is also discussed by considering the effects of parasitic and non-idealities of the used active element. Additionally, higher order filter realisation is also included to enrich the presented work by exploring possible applicability aspects. The theoretical performance is validated at schematic level using 0.18 µm CMOS technology parameters with ±1 V supply voltages. Furthermore, Cadence Analog Design Environment (ADE) with gpdk 0.18 µm technology is used to design the layout of the proposed circuit. Pre-layout and post-layout simulation verification is provided to extend the real time validation of theoretical aspects.
一种新型CMOS兼容高性能一阶全通滤波器的实现
本文提出了一种具有低电压、低功耗特点的电子可调谐一阶电压型全通滤波器的新实现。所提出的滤波器实现仅采用一个有源元件,即差分电压+ x电流控制输送机和一个接地电容器。从芯片制造的角度来看,使用最少数量的元件使所提出的结构简单而有吸引力。本文还讨论了所提出结构的性能,考虑了所使用的有源元件的寄生和非理想性的影响。此外,还包括高阶滤波器的实现,通过探索可能的适用性方面来丰富所提出的工作。在±1 V电源电压下,采用0.18µm CMOS技术参数,在原理图级验证了理论性能。此外,采用gpdk 0.18µm技术的Cadence模拟设计环境(ADE)来设计所提出电路的布局。提供了布局前和布局后的仿真验证,扩展了理论方面的实时验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Australian Journal of Electrical and Electronics Engineering
Australian Journal of Electrical and Electronics Engineering Engineering-Electrical and Electronic Engineering
CiteScore
2.30
自引率
0.00%
发文量
46
期刊介绍: Engineers Australia journal and conference papers.
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