A high performance 0.13 /spl mu/m CMOS process for GHz microprocessor manufacture

Abstract

A highly manufacturable and high performance 0.13 /spl mu/m CMOS process for a 1.5 V microprocessor is proposed. The device is integrated by dual-doped poly-Si transistors with STI, additionally doped gate poly, highly doped drain extension and Co-salicide structure. Co-salicide gate with sheet resistance below 5 ohm/sq. in the 0.1 /spl mu/m -length gate line is obtained. By using indium and boron as channel implants, and employing n/sup +/poly gates for nMOS while low-energy boron instead of BF2 is used for pMOS gates, the Idsat values of 770 /spl mu/A//spl mu/m and 31 /spl mu/A//spl mu/m have been achieved with the electrical gate oxide thickness of 2.6 nm and 2.8 nm for nMOS and pMOS, respectively.