Fan-Out Chip on Substrate Device Interconnection Reliability Analysis

Abstract

Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electrical performance in multi-die connection,. The multiple re-distribution layer (RDL) processing is implemented in advance multi-dies FO chip on substrate device for die to die connection meeting higher density electronic connection need. And for complex function request, the area of side-by-side silicon dies size are very close to FO multi-dies chip size, there is narrow die gap between these side-by-side dies. A large coefficient of thermal expansion (CTE) mismatch between epoxy molding compound (EMC) and silicon dies is a significant contributor to the origin of warpage, and will lead to high thermal-mechanical strain and stress at narrow area of side-by-side die gap. The redistribution layer could be high stress risk site by the high thermal-mechanical stress on narrow side-by-side dies gap area. This study is to build a fan-out chip on substrate package numerical simulation model by finite element method (FEM) and get good warpage and thermal-mechanical strain correlation between simulation and real package measurement result by advance Metrology Analyzer (aMA) system. Then we used this equivalent numerical model to compare the thermal-mechanical performance for different redistribution layer pattern design. Finally, generalizing the redistribution layer pattern design guideline and to enhance the package level reliability performance, especially under temperature cycling test (TCT) condition, of fan-out chip on substrate package. The new redistribution layer pattern layout can pass 1000 temperature cycling test cycles and there is lower stress risk on redistribution layer.