Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC

Abstract

This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs to generate thermometer code without using comparators. The design supports Dynamic Voltage Frequency Scaling. Binary-weighted TFET device sizing is used to generate thermometer code. TFETs used in this work are compatible with a 28nm FDSOI-CMOS process for fabrication. The most relevant performance numbers for 3- to 10-bit ADC architectures include speed of operation of 68 MHz with an ENOB evaluated greater than 2.38 for the 3-bit ADC; the FOM is in the range of 0.07 to 1.3 fJ/conversion for 3- to 10-bit designs with supply voltages from 0.4V to 1.2V, respectively. The proposed 5- and 6-bit designs show 46x [1] and 265x [2] improvement in FOM, respectively.