A turbo/MAP decoder for use in satellite circuits

Abstract

The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E/sub b//N/sub 0/ of 0.32 and -0.30 dB, respectively for a BER of 10/sup -5/. BERs down to 10/sup -7/ were also achieved for a small increase in E/sub b//N/sub 0/.