A −117dBc THD (−132dBc HD3) and 126dB DR Audio Decoder with Code-Change-Insensitive RT-DEM Algorithm and Circuit Technique for Relaxing Velocity Saturation Effect of Poly Resistors

Abstract

Three major distortion sources in high-fidelity audio decoders are 1) DAC inter-symbol interference (ISI) [1], [2]; 2) 3rd-order harmonic distortion (HD3) due to the 2nd-order nonlinearity of poly resistors; and 3) Cross-over distortion (COD) arising from limited amplifier inner-loop gain due to high output load capacitance (CL) [3], [4]. First, to alleviate the ISI, [1] presents a Real-Time Dynamic-Element-Matching (RT-DEM) algorithm to realize mismatch shaping for DAC cells, achieving 115dB SFDR without complex digital hardware as in [2]. However, the constraint of 1-LSB change with the RT-DEM limits dynamic range (DR) of the $\Delta\Sigma$ modulator. Moreover, a high clock rate of 181 MHz causes a high power consumption. Second, with a large signal swing, the total harmonic distortion (THD) of current-to-voltage (I2V) amplifiers is frequently dominated by the HD3 in [1]–[5]. The potential cause of this HD3 is due to the velocity saturation effect (VSE) of poly resistors [6]. Lastly, for a large load capacitance, the damping-factor-control frequency compensation (DFCFC) is commonly applied in multi-stage amplifiers to enhance the stability [4], [5]. However, it degrades the amplifier inner-loop gain and causes severe COD. In [4], a compensation scheme inserts a gain stage inside the inner loop to boost the loop gain over the audio band (20Hz to 20kHz), suppressing the peak COD below −111 dBc. In this work, three techniques are presented to eliminate the aforementioned distortion sources: 1) a code-change-insensitive RT-DEM (CCI-RT-DEM) algorithm is introduced to dynamically select the new start index of rotated DAC cells for the next code, instead of the fixed index at the first one [1], thus allowing for more than 1-LSB change; 2) a poly-resistor linearization scheme is presented to suppress HD3 by mitigating the VSE of resistors; and 3) a 2nd-order DFCFC for multi-stage amplifiers is introduced that allows a high inner-loop gain to suppress the COD, thus enhancing the amplifier linearity even with a large CL. Combining these solutions, the DAC and amplifier together achieve −117dBc THD (−132dBc HD3) and 126dB DR.