Skew Sensitivity Minimization Of Buffered Clock Tree

J. Chung, Chung-Kuan Cheng
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引用次数: 33

Abstract

Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduces the interconnect length. For a given clock tree of n points and a library of s different buffer sizes, the run time of the presented algorithm is O(log3ns2). Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm.
缓冲时钟树的倾斜灵敏度最小化
在给定时钟树拓扑结构和缓冲区库的情况下,提出了一种利用动态规划方法实现倾斜灵敏度最小化的有效算法。我们的算法找到了最优的缓冲大小,它在时钟树中的插入水平,以及最优的导线宽度,以最小化生产变化下的倾斜灵敏度。通过在最后阶段移动缓冲位置进行仔细的微调,保留了最小的倾斜灵敏度特性并减少了互连长度。对于给定的n个点的时钟树和s个不同缓冲区大小的库,本文算法的运行时间为O(log3n•s2)。实验结果表明,与应用该算法之前相比,时钟偏差显著降低了87 ~ 144倍。我们还观察到,由于应用了所提出的倾斜灵敏度算法,时钟信号的传播延迟进一步降低。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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