A BIST scheme for testing DAC

Abstract

In this paper, we propose a low speed built-in-self-test (BIST) scheme for testing static parameters of high-speed digital-to-analog converter (DAC). Based on under-sampling technique, the DAC output signal is modulated into low speed pulse signal by pulse-width-modulation (PWM) with two sinusoidal carriers. The nonlinearity errors of DAC hence represents on duty ratio of converted pulse signal. In addition, a precise embedded time-to-digital converter (TDC) is inserted to measure the pulse width of converted signal on chip. The static parameters of DAC then can be estimated through analyzing output signal of TDC captured by conventional logic analyzer. To demonstrate the proposed scheme, we applied the method on 8-bits 200MS/s DAC. The experiment showed very good result that the maximum estimated error of DNL and INL are less than 0.2LSB and 0.35LSB. Moreover, the most important merit is that the required test environment and equipment are low speed compared to DAC under test.