Fused RRAM-Based Shift-Add Architecture for Efficient Hyperdimensional Computing Paradigm

Abstract

Memristor-based implementations promises efficient in-memory computing architectures. Hence, it has been extensively utilized as multiply-and-add accelerator engines in signal processing and artificial intelligence applications. Hyperdimensional computing (HDC) paradigm is an encouraging brain-inspired computational framework that performs computations on hyperdimensional vectors. The encoding operation in HDC takes about 80% of the execution time and consists of multi-plication, addition and shifting. In this paper, a reconfigurable memristor array is used to implement in-memory shifting and addition to the seeds of the hyperdimensional vectors. The presented scheme fuses the circular shifting with summation operations. This is the first work to introduce such scheme and it provides savings in time, power and area compared to traditional computations and other crossbar approaches that performs separate operations on the crossbar. Spice simulation of the proposed scheme using 65nm foundry has been used to verify the functionality.