Dynamic clock management for low power applications in FPGAs

I. Brynjolfson, Z. Zilic
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引用次数: 46

Abstract

Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management.
fpga低功耗应用的动态时钟管理
采用动态控制时钟速率的低功耗技术提供了潜在的强大节能能力。在本文中,我们考虑将这种低功耗技术应用于fpga,从而减少时钟分布中的能量浪费。我们表明当前的FPGA时钟管理器不适合在动态控制系统中使用。我们提供了一个架构块——动态时钟分配器,它既可以在内部添加到时钟管理器中,也可以作为用户逻辑添加到时钟管理器中,从而实现动态时钟管理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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