A fabrication method for high performance embedded DRAM of 0.18 /spl mu/m generation and beyond

Abstract

A new fabrication method for embedded DRAM of 0.18 /spl mu/m generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned Salicide Block (SSB), a new process technology. Fabricated embedded DRAM shows excellent characteristics with respect to both retention time and MOSFET AC/DC performance, promising high performance of SOC (System On a Chip) applications.