{"title":"Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor","authors":"A. Gaidhane, G. Pahwa, A. Verma, Y. Chauhan","doi":"10.1109/icee44586.2018.8937923","DOIUrl":null,"url":null,"abstract":"A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper. We propose an explicit continuous formulation of the drain current in terms of an intermediate parameter which is solved using a compact modeling approach. The proposed model captures a wide range of ferroelectric material parameter variations of a DG-NCFET in the non-hysteretic regime of operation. We implement our compact model in Verilog-A code and validate extensively with TCAD simulation results. We test the transient capability of the proposed model by simulating NCFET based 15-stage ring oscillator in a commercial circuit simulator.","PeriodicalId":6590,"journal":{"name":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","volume":"69 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icee44586.2018.8937923","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A surface potential based compact model for a long channel MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type Double Gate Negative Capacitance transistor (DG-NCFET) is presented in this paper. We propose an explicit continuous formulation of the drain current in terms of an intermediate parameter which is solved using a compact modeling approach. The proposed model captures a wide range of ferroelectric material parameter variations of a DG-NCFET in the non-hysteretic regime of operation. We implement our compact model in Verilog-A code and validate extensively with TCAD simulation results. We test the transient capability of the proposed model by simulating NCFET based 15-stage ring oscillator in a commercial circuit simulator.