ESD-immunity Study of High-voltage nLDMOS with Vertical Parasitic Schottky Structures in the Source End

Abstract

In this paper, a TSMC $0.18- {\mu} \mathrm{m}$ BCD process is used to realize high-voltage n-LDMOS devices. And then, the source side $n^{{+}}$ layer of the reference device is removed, so that the source terminal will make a parasitic Schottky device. Next, in this paper, we will evaluate its impacts on the discharge current capability. There are four kinds of tested devices in this work, which are the reference, with whole source -Schottky MM, and removed half source electrode MN and maked half Schottky in source end NM type devices, respectively. According to the TLP testing results, three important values of snapback curve can be obtained: trigger voltage (${\mathrm{V}}_{{\mathrm t1}}$), holding voltage (${\mathrm{V}}_{{\mathrm{h}}}$), and secondary breakdown current (${\mathrm{I}}_{{\mathrm{t}}2}$). Finally, it can be concluded that if a Schottky device is added to the source terminal, the on-resistance will be increased due to the series connection of this Schottky device, then the trigger voltage can be increased about 2V and holding voltage increased about 8V.