A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-04-12 DOI:10.1109/ISSCC.2018.8310321

H. Maejima, K. Kanda, Susumu Fujimura, Teruo Takagiwa, S. Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, R. Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Y. Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, M. Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, N. Kobayashi, M. Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Y. Ochi, Kenro Kubota, T. Wakui, D. He, Weihan Wang, H. Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Y. Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, T. Futatsuyama, K. Hosono, N. Shibata, Toshiki Hisada, T. Kaneko, H. Nakamura

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引用次数: 5

Abstract

The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart Vt-tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.

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采用96字行层技术的512Gb 3b/Cell 3D闪存

2007年，第一个多层堆叠3D闪存被提出为BiCS Flash[1]。从那时起，由于不断的3D技术创新导致堆叠层数量的增加，内存位密度迅速增长。另一方面，最初提出用于2D闪存的多层单元技术也被用于3D闪存。第一个3b/cell 32层Flash于2015年发布[2]，随后在2016年发布了48层Flash[3]，在2017年发布了64层Flash[4,5]。本文介绍了一种采用96字行层BiCS Flash技术的512Gb 3b/cell 3D闪存。本文实现了提高性能的三个关键技术:(1)基于字符串的启动偏置控制方案使程序时间缩短了7%;(2)智能vt跟踪读取通过最小化跟踪时间和支持程序挂起读取功能来提高读重试性能;(3)低预充电感测放大器总线方案将感测放大器与数据缓存之间的功耗和数据传输时间降低了一半。图20.1.1显示了芯片显微图和芯片主要特征的总结。

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2018 IEEE International Solid - State Circuits Conference - (ISSCC)

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