A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications

Daming Zhang, Shuangchen Li, Yongpan Liu, X. Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang
{"title":"A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications","authors":"Daming Zhang, Shuangchen Li, Yongpan Liu, X. Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang","doi":"10.1145/2797135","DOIUrl":null,"url":null,"abstract":"Developing circuits for streaming applications written in C (or its variants) can benefit greatly from C-to-RTL (C2RTL) synthesis. Yet, most existing C2RTL tools lack system-level options to trade off various design constraints, such as delay and area. This article introduces a systematic way to accomplish C2RTL synthesis for streaming applications containing thousands of lines of C (or its variants) codes. Synthesizing circuits for such large applications presents serious challenges for existing C2RTL tools. Specifically, the proposed approach determines simultaneously the number of pipeline stages and the number of times that each functional block is duplicated in each pipeline stage. A mixed integer linear programming-based solution is formulated for obtaining the optimal solution. Furthermore, a heuristic algorithm is developed for large-scale problems. To accommodate the differences of the data rates between the adjacent hardware modules, first-in-first-out (FIFO) buffers are indispensable, but their overheads are nonnegligible. A parallelism-aware FIFO sizing method is also introduced to determine the optimal sizes of FIFOs. Experimental results on seven real-world applications demonstrate that the algorithms in the synthesis flow can make effective design trade-offs and find superior solutions in a short time compared with existing approaches. Furthermore, the algorithms achieve optimal results in most cases with subsecond running time.","PeriodicalId":7063,"journal":{"name":"ACM Trans. Design Autom. Electr. Syst.","volume":"77 1","pages":"19:1-19:32"},"PeriodicalIF":0.0000,"publicationDate":"2016-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Trans. Design Autom. Electr. Syst.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2797135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Developing circuits for streaming applications written in C (or its variants) can benefit greatly from C-to-RTL (C2RTL) synthesis. Yet, most existing C2RTL tools lack system-level options to trade off various design constraints, such as delay and area. This article introduces a systematic way to accomplish C2RTL synthesis for streaming applications containing thousands of lines of C (or its variants) codes. Synthesizing circuits for such large applications presents serious challenges for existing C2RTL tools. Specifically, the proposed approach determines simultaneously the number of pipeline stages and the number of times that each functional block is duplicated in each pipeline stage. A mixed integer linear programming-based solution is formulated for obtaining the optimal solution. Furthermore, a heuristic algorithm is developed for large-scale problems. To accommodate the differences of the data rates between the adjacent hardware modules, first-in-first-out (FIFO) buffers are indispensable, but their overheads are nonnegligible. A parallelism-aware FIFO sizing method is also introduced to determine the optimal sizes of FIFOs. Experimental results on seven real-world applications demonstrate that the algorithms in the synthesis flow can make effective design trade-offs and find superior solutions in a short time compared with existing approaches. Furthermore, the algorithms achieve optimal results in most cases with subsecond running time.
支持流应用程序分区、并行化和FIFO分级的C2RTL框架
为用C(或其变体)编写的流应用程序开发电路可以从C-to- rtl (C2RTL)合成中受益匪浅。然而,大多数现有的C2RTL工具缺乏系统级选项来权衡各种设计约束,例如延迟和面积。本文介绍了为包含数千行C(或其变体)代码的流应用程序完成C2RTL合成的系统方法。如此大型应用的合成电路对现有的C2RTL工具提出了严峻的挑战。具体来说,所提出的方法同时确定了管道阶段的数量和每个功能块在每个管道阶段中重复的次数。给出了求解最优解的混合整数线性规划方法。在此基础上,提出了一种求解大规模问题的启发式算法。为了适应相邻硬件模块之间数据速率的差异,先进先出(FIFO)缓冲区是必不可少的,但它们的开销不可忽略。引入了一种并行感知的FIFO分级方法来确定FIFO的最优大小。七个实际应用的实验结果表明,与现有方法相比,综合流程中的算法可以有效地进行设计权衡,并在短时间内找到更优的解决方案。此外,算法在大多数情况下以亚秒级的运行时间获得最优结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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