Machine Learning Algorithms Performance Analysis for VLSI IC Design

J. Chen, Kong-Long Lai
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Abstract

The design of an analogue IC layout is a time-consuming and manual process. Despite several studies in the sector, some geometric restrictions have resulted in disadvantages in the process of automated analogue IC layout design. As a result, analogue design has a performance lag when compared to manual design. This prevents the deployment of a large range of automated tools. With the recent technical developments, this challenge is resolved using machine learning techniques. This study investigates performance-driven placement in the VLSI IC design process, as well as analogue IC performance prediction by utilizing various machine learning approaches. Further, several amplifier designs are simulated. From the simulation results, it is evident that, when compared to the manual layout, an improved performance is obtained by using the proposed approach.
VLSI集成电路设计中的机器学习算法性能分析
模拟IC版图的设计是一个耗时且人工的过程。尽管在该领域进行了一些研究,但一些几何限制导致了自动化模拟IC布局设计过程中的缺点。因此,与手动设计相比,模拟设计具有性能滞后。这阻碍了大量自动化工具的部署。随着最近技术的发展,这一挑战可以通过机器学习技术来解决。本研究探讨了VLSI IC设计过程中性能驱动的放置,以及利用各种机器学习方法进行模拟IC性能预测。此外,还对几种放大器设计进行了仿真。仿真结果表明,与手工布局相比,该方法的性能得到了显著提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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