Implementation of High Speed and Low Power Carry Select Adder with BEC

Abstract

One of the most substantial areas of research in VLSI is the design of power-efficient and high-speed data path logic systems. The speed of addition is constrained in digital adders by the time taken to propagate a carry through the adder. When the previous bit has been added and the carry generated from this addition is propagated onto the next bit, the sum for each bit in an elementary adder is generated sequentially in this manner. In several computer systems, the Carry Select Adder (CSLA) is used to mitigate the issue of carry propagation delay by generating multiple carry bits and then selecting a carry for the desired output. The CSLA, however, is not area-efficient since it utilizes several Ripple Carry Adders (RCA) pairs to produce partial sum and carry by considering carry data, and then multiplexers pick the final sum and carry (mux). The core concept of this study is to use the Binary to Excess-1 Converter (BEC) to achieve high speed and low-power consumption instead of the RCA in the regular CSLA. The results have been analyzed and compared for implementation of three adders (conventional CSA, CSA with RCA, CSA with BEC). The results from the performance evaluations of the adders are compared with each other. All the simulation is carried out in 45nm technology. The delay of CSA and CSA with RCA are same, but the main difference is in reduction of area and power. Similarly when CSA(BEC) and CSA(RCA) are compared, the area has been reduced by approximately 18.67% and power has been reduced by 25.85%.