Yield and performance improvement through technology-design co-optimization in advanced technology nodes

Yue Liang
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引用次数: 2

Abstract

As Si technology advances along with more complex fabrication process, new challenges arise during the advanced technology bring-up stage, especially due to convoluted interaction among process, device and circuit. New test structures and technology bring-up methodologies are necessary to account for process induced variation. Layout and circuit design need to be optimized to mitigate the process impact. This talk discusses these challenges and current approaches to address them.
通过先进技术节点的技术设计协同优化来提高产量和性能
随着硅技术的进步和制造工艺的复杂化,在先进技术的培养阶段出现了新的挑战,特别是由于工艺,器件和电路之间复杂的相互作用。新的测试结构和技术提出方法是必要的,以解释过程引起的变化。需要优化布局和电路设计以减轻工艺影响。本次演讲将讨论这些挑战以及当前解决这些挑战的方法。
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