A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC

Abstract

In this paper, a Silicon On Thin Buried-oxide (SOTB) implementation of the 32-bit floating-point Twiddle Factor (TF) is presented. The architecture was developed based on the adaptive COordinate Rotation DIgital Computer (CORDIC). The CORDIC method is a well-known approach for approximating the complex-number multiplication, also known as TF in Fast Fourier Transform (FFT) designs. The SOTB-65nm TF core layout has the size area of 86.7K-µm2. The measurement results showed that at the best crossing-point of the 0.75-V power supply (VDD), the chip could run at the maximum operating frequency (FMax) of 32-MHz and consumed 181-µW power. At the sleep-mode, the leakage power dropped about 258.6× to 0.7-µW at the 0.75-V VDD.