Design and Implementation of Link Layer Based on JESD204B Protocol

Abstract

Interface protocol JESD204B can support 12.5 Gbit/s serial transmission rate, which can solve the problem of high-speed data transmission between data converter and logic device. In this paper, the link layer of sender and receiver based on JESD204B protocol is designed with Verilog HDL, and the feasibility of the design is verified by Xilinx ZYNQ7000 series development board and AD9375 rf board. The comprehensive results show that the data link layer implemented in this scheme can meet the protocol requirements, realize the normal transmission of data, and greatly reduce the consumption of resources. It has the characteristics of universality and portability.