0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur

Abstract

This paper presents an injection-locked PLL that employs RC pulse generator and injection timing calibration to enhance the jitter and reference spur performance. An ultra-low power oscillator is designed to reduce the overall power consumption of the PLL. The chip is fabricated in 65nm CMOS technology, occupying an area of 0.25mm2. The proposed ILPLL achieves 70fsrms integrated jitter and -66dBc reference spur, while consuming 0.2mW, which translates into -270dB FoM at 2.4GHz output frequency.