A VLSI architecture for multidimensional DFT computation

Abstract

The authors describe the design of a systolic array processing element for use in multidimensional DFT (discrete Fourier transform) computation, using a suitable mapping technique, with a bit-serial approach, for implementation in VLSI, in a semicustom CAD (computer-aided design) tool environment. They investigate appropriate algorithms for computation of the DFT as well as VLSI architectures that the DFT algorithms may be mapped onto, and a mapping technique for multidimensional time systems onto VLSI architectures.<>