On-chip probes for silicon defectivity ranking and mapping

Abstract

We present process probes useful to investigate the process-dependent quality of p-n junctions in semiconductors. The probes are sensitive to the presence of thermal generation centers, which ignite macroscopic current avalanches. Since the carrier generation events are promoted by the presence of localized imperfections such as dislocations, stacking faults, etc., the avalanche ignition rate represents a suitable figure of merit for ranking the overall process cleanliness. In particular, by using these probes we report a nonuniform distribution of lattice defects within certain junctions. This phenomenon has been verified by means of standard etching and infrared optical inspection. Some technological hints are finally provided, capable of reducing the defectivity and improving the fabrication of microelectronic devices.