Phase noise improvement for array systems

Shilei Hao, T. Hu, Q. Gu
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引用次数: 4

Abstract

This paper demonstrates a phase noise improvement technique for array systems by using the phase noise filter (PNF) and the noise's uncorrelated feature. The PNF aims to suppress input signal phase noise, which is however constrained by the PNF's own circuit noise, named as the phase noise sensitivity. In array systems, the noise from each individual PNF are uncorrelated, while the input signal and noise are correlated. By leveraging this feature, the phase noise in array systems will be theoretically improved by 10×log(N), where N is the element number of the array. Both simulation and 2-element array measurement results verify this theory. In the demonstration, the phase noise of 2-element PNF array is improved to -118 dBc/Hz at 1 MHz offset for a 10 GHz clock from the single PNF's sensitivity of -116.1/-115.4 dBc/Hz, respectively. The improvement is 2-3 dB, which is very close to the theoretical value. The phase noise suppression level and input frequency range are similar to the single PNF. The demonstrated -118 dBc/Hz at 1 MHz offset for a 10 GHz clock is the best result in the CMOS process based on the authors' best knowledge.
阵列系统相位噪声的改进
本文介绍了一种利用相位噪声滤波器(PNF)和噪声的不相关特性来改善阵列系统相位噪声的技术。PNF的目的是抑制输入信号的相位噪声,但相位噪声受PNF自身电路噪声的限制,称为相位噪声灵敏度。在阵列系统中,来自各个PNF的噪声是不相关的,而输入信号和噪声是相关的。利用这一特性,阵列系统中的相位噪声理论上可以通过10×log(N)得到改善,其中N为阵列的单元号。仿真和二元阵列测量结果验证了这一理论。在演示中,2元PNF阵列的相位噪声分别从单个PNF的-116.1/-115.4 dBc/Hz的灵敏度提高到-118 dBc/Hz,在1 MHz偏移为10 GHz时钟。改进幅度为2-3 dB,非常接近理论值。相位噪声抑制水平和输入频率范围与单PNF相似。基于作者的最佳知识,演示了10ghz时钟在1mhz偏置下-118 dBc/Hz的最佳结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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