A fully-digital phase-locked low dropout regulator in 32nm CMOS

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243833

A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De

引用次数: 16

Abstract

A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).

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32nm CMOS全数字锁相低差稳压器

采用32nm CMOS设计了一种全数字锁相低差稳压器(LDO)，用于向多vcc数字电路提供细粒度功率。在广泛的输入电压和电流范围内的测量表明，LDO具有出色的负载调节能力，在标称负载电流条件下(ILOAD=3mA)，其效率接近理想效率的97%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2012 Symposium on VLSI Circuits (VLSIC)

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