{"title":"Efficient hardware-oriented cellular active contours","authors":"D. L. Vilariño, C. Rekeczky","doi":"10.1109/ISCAS.2004.1328676","DOIUrl":null,"url":null,"abstract":"In this paper, an improved algorithm for the cellular active contour technique called pixel-level snakes is proposed. The motivation is twofold: on the one hand a higher efficiency and flexibility in the contour evolution towards the boundaries of interest is pursued. On the other hand a higher performance and suitability for its hardware implementation onto a CNN chip-set architecture is required. To illustrate the validity of the proposal some examples and data about the computation time from the implementation of the algorithm on the 64/spl times/64 CNNUM chip have been included.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"09 1","pages":"III-33"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2004.1328676","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, an improved algorithm for the cellular active contour technique called pixel-level snakes is proposed. The motivation is twofold: on the one hand a higher efficiency and flexibility in the contour evolution towards the boundaries of interest is pursued. On the other hand a higher performance and suitability for its hardware implementation onto a CNN chip-set architecture is required. To illustrate the validity of the proposal some examples and data about the computation time from the implementation of the algorithm on the 64/spl times/64 CNNUM chip have been included.