Using ant colony optimization for test vector reordering

Abstract

The increasing complexity of chip design has posed great challenge for low power SoC test. Test vector reordering technique can lower circuit power dissipation. This paper proposes a new approach to low power SoC test based on ant colony optimization to find the optimal orders for test vector application. Experimental results on benchmark ITC'02 demonstrate the average improvement of 12.3% over the existing methods.