Parallel 3D deterministic particle transport on Intel MIC architecture

2014 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2014-09-22 DOI:10.1109/HPCSim.2014.6903685

Qinglin Wang, Zuocheng Xing, Jie Liu, X. Qiang, Chunye Gong, Jiang Jiang

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引用次数: 4

Abstract

Single-node computation speed is essential in large-scale parallel solutions of particle transport problems. The Intel Many Integrated Core (MIC) architecture supports more than 200 hardware threads as well as 512-bit double precision float-point vector operations. In this paper, we use the native model of MIC in the parallelization of the simulation of one energy group time-independent deterministic discrete ordinates particle transport in 3D Cartesian geometry (Sweep3D). The implementation adopts both hardware threads and vector units in MIC to efficiently exploit multi-level parallelism in the discrete ordinates method when keeping good data locality. Our optimized implementation is verified on target MIC and can provide up to 1.99 times speedup based on the original MPI code on Intel Xeon E5-2660 CPU when flux fixup is off. Compared with the prior on NVIDIA Tesla M2050 GPU, the speedup of up to 1.23 times is obtained. In addition, the difference between the implementations on MIC and GPU is discussed as well.

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基于Intel MIC架构的并行三维确定性粒子输运

在粒子输运问题的大规模并行解中，单节点计算速度至关重要。Intel多集成核心(MIC)架构支持200多个硬件线程以及512位双精度浮点向量操作。在本文中，我们使用MIC的原生模型来并行化模拟三维笛卡尔几何中一能量群时间无关的确定性离散坐标粒子输运(Sweep3D)。该实现在保证数据局部性的前提下，同时采用了硬件线程和MIC中的矢量单元，有效地利用了离散坐标法中的多级并行性。我们的优化实现在目标MIC上进行了验证，当通量修复关闭时，基于Intel Xeon E5-2660 CPU上的原始MPI代码，可以提供高达1.99倍的加速。与之前的NVIDIA Tesla M2050 GPU相比，获得了高达1.23倍的加速。此外，还讨论了在MIC和GPU上实现的不同之处。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2014 International Conference on High Performance Computing & Simulation (HPCS)

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