A duty cycle control circuit for high speed applications

Abstract

An accurate and programmable CMOS duty-cycle control (DCC) circuit for high-speed applications is discussed. Proposed DCC circuit has a first order transfer function the accuracy of which is just limited by the on-chip device mismatch. Operating at 1GHz frequency, the duty-cycle of the output clock can be tuned between 45 to 60% by changing the charge and discharge currents of a charged-pump circuit (CPC). CPC's current is controlled through five controlling bits. The circuit is designed in a 0.18/spl mu/m CMOS technology and draws 160/spl mu/A from a 1.8V supply with less than 0.3/spl times/LSB error.