An on-line testing scheme for repairing purposes in Flash memories

Abstract

The constant evolution of technologies involves a large amount of problems during and after Flash memory manufacturing. In this context, manufacturers must develop methods and design solutions to improve reliability especially for automotive applications. For this purpose, ECC and BISR are probably the most efficient concepts to enhance memory reliability. However, such techniques are limited to correct errors occurring punctually within a word whereas in memories the stress of peripheral circuit can lead to an entire faulty bit or word line. This phenomenon is referred as Clustering Effect. This work proposes an on-line testing structure for clustering effects according to the word line plan. This test structure allows achieving a test time acceptable and is shown as low cost in term of surface overhead (3 HV transistors, 1 XOR, 1 MUX and 1 DFF). Adding our solution to recent ECC and BISR techniques, spatial or automotive applications could be easily targeted.