A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching

Abstract

A novel ΔΣ time-to-digital converter (TDC) with a time mode accumulator and a multi-bit quantizer is proposed in this work. Measurement time is reduced when compared with single-bit ΔΣ TDCs. A time difference adder consisting of gated delay-line based time-registers is used to serve as the time accumulator. A dynamic element matching algorithm is implemented to mitigate the performance loss degraded by the non-linearity of the multi-bit quantizer. The TDC is designed and simulated using a 65nm CMOS process and operates at a 100MHz sampling rate. For a 1.25MHz bandwidth, 108fsrms integrated noise or 2.4ps equivalent resolution is achieved. The power consumption is only 0.45 mW and the figure of merit (FoM) is calculated to be 154fJ/step.