Reduction of common mode voltage in three phase inverter

Abstract

Pulse Width Modulated (PWM) inverters produce common mode voltage. The common mode voltage will have adverse effect on the motor bearings. Hence the common mode voltage has to be reduced. This paper presents a modified Sinusoidal Pulse Width Modulation (SPWM) scheme in which two complementary modulating inputs are used to generate the pulses for the switches of a two level, three phase inverter to reduce the common mode voltage. The performance of proposed modulation scheme is evaluated and tested for various switching frequencies. With the proposed modulation scheme the phase voltages appears to be three level voltage which helps in reduction of common mode voltage. A comparative study of common mode voltage with both normal and modified SPWM method is also done and the results are presented in this paper.