Optimization of embedded SiGe process to enhance PFET performance on 28nm low power platform

Abstract

This paper presents a new SiGe profile of 28nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class 27nm pFET transistor. PFET Drive current of 431 μA/μm at off current 7.5×l0−10A/μm were achieved at Vd = -1.05V, which performance is 12% higher than standard SiGe structure. TCAD simulation reveals that compressive stress intensity of modified SiGe is ~3% higher than that of standard SiGe. The effective mobility curves are obtained by split CV method, the mobility peak value of modified SiGe is also higher. This reveals compressive stress induced in the channel and decreasing parasitic resistance in SD region by modified SiGe structure are shown to be the major source of the observed performance enhancement. This research about pFET performance boosting through SiGe profile modification has given an optimized direction for mass production in 28nm platform.