Asymmetrical FinFET SRAM cells with wider read noise margin and lower leakage currents

Abstract

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new FinFET memory circuits with asymmetrically gate underlap engineered transistors are proposed in this paper for achieving stronger read data stability and lower leakage power consumption. With the proposed asymmetrical six-transistor SRAM cells, read data stability is enhanced by up to 72.2% while maintaining similar write voltage margin and layout area as compared to the conventional symmetrical six-transistor SRAM cells in a 15nm FinFET technology. Furthermore, leakage power consumption is reduced by up to 37.4% with the proposed asymmetrical FinFET SRAM cells as compared to the conventional six-FinFET SRAM cells with symmetrical transistors.