Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders

Abstract

Carry tree sparseness is used in high-performance binary adders to achieve better energy-delay trade-off. To determine the energy optimal degree of sparseness, a detailed analysis is performed in this work. An analytical expression for the upper bound of sparseness is derived. The effect of increased sparseness on partial sum block and total energy is explored on 32-, 64-, 128-, and 256-bit adders. Higher degrees of sparseness in the carry generation block is achieved by employing parallel adders in the sum block instead of serial ripple carry adders. 64-bit adders with various sparseness degrees using leading addition algorithms are synthesized and optimized with a standard cell library in 45nm CMOS technology. Post layout simulations revealed that the optimal sparse carry tree adders provide up to 50% and 22% improvement in energy at same performance over full carry tree Kogge-Stone and Ladner-Fischer adder designs, respectively.