A 14.6mW 12b 800MS/s 4×time-interleaved pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration

Abstract

A 12b time-interleaved pipelined SAR ADC is presented. The proposed sampling circuit makes timing skew immune to mismatch of control circuit for time interleaving and reduces the main mismatch source to only sampling switch to achieve very low sampling skew of 60fsrms without calibration. MDAC transfer curve of pipeline stage is folded and OP output is kept half without degrading its gain and bandwidth by the proposed MDAC. The proposed OP loading reset scheme also enhances the settling speed without sacrificing ADC conversion time. Operating at 800MS/s, this ADC consumes 14.6mW from 1V supply and achieves SNDR of 60.8dB with Nyquist input.