A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme

Abstract

A 20 bit delta sigma A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply. It provides a 25 kHz data rate for high speed DC measurement while maintaining good performance required by accurate DC measurement such as noise, linearity and drift. The front-end programmable gain amplifier allows the users to optimize their system with different ranges of input level. Offset and finite gain compensation technique is used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta sigma converter section, low frequency error reduction is achieved through chopper stabilization technique. A novel frequency-shaped chopper stabilization scheme is used to alleviate the inter-modulation tone which commonly exists due to the use of fix frequency chopping in delta sigma modulators. This A/D converter achieves 2.8 ppm RMS noise and 12 ppm INL at a gain of one.