Implementation of Power Efficient Dynamic Comparator at 180 nm Process Technology for high-speed applications

Abstract

This paper divulges an advanced dynamic model of comparator that contributes towards fast-rate of comparison, better slew-rate and lesser amount of power consumption. The preamplifier referred dynamic technique in comparators is extensively utilized in analogue to digital converters (ADCs). It provides positive feedback technique to rejuvenate the signal from analogue to full sway digital. When the output of preamplifier phase approaches to power supply, the added power is consumed by the overall circuit. In the proposed implementation of comparator model, the voltage swaying of preamplifier phase is restricted to one-half of the power supply. The new technique gives rise to lesser power and has high slew-rate. This paper depicts the comparison between separate dynamic comparator models. The simulation result is carried out using Pyxis tool (Mentor Graphics) in 180nm technology.