Low power and high speed computation using hybridized multiplier

Abstract

The key problems in designing of VLSI circuits are high power consumption, larger area utilization and delay which affect the speed of the computation and also results in power dissipation. In general speed and power are the essential factors in VLSI design. For solving the issues, a new architecture has been proposed. In the proposed system, the two high speed multipliers, Modified booth multiplier (MBM) and the Wallace tree multiplier are hybridized with Carry Look Ahead adder (CLA) and formed a hybridized multiplier which delivers high speed computation with low power consumption. MBM is proposed to reduce the partial products whereas Wallace tree multiplier is accompanied for fast addition and CLA is used for final accumulation. This hybrid multiplier produces better results in terms of speed and power than the conventional designs. The simulation results prove that the hybrid architecture is superior to other multipliers. It is done by using Xilinx tool and it is implemented using FPGA (Field Programmable Gate Array).