Time-domain simulation of variational interconnect models

Abstract

Interconnect parameter variations are more significant in the nanometer regime due to the increase in relative tolerances for upcoming integration technologies. As several variability studies indicate the significant role of the interconnect on system performance, the analysis of linear models is extremely crucial. Contrary to devices, the extreme case scenarios do not apply for context-dependent interconnect, necessitating a statistical analysis framework. A previously proposed approach to represent interconnect models in terms of global interconnect parameters is necessary in such frameworks. In this paper we present efficient ways of simulating these variational interconnect models in the presence of nonlinear devices. We demonstrate our methodology by incorporating variational interconnect models into transistor-level simulation with accurate nonlinear device models.