Mobility enhancement due to charge trapping & defect generation: Physics of self-compensated BTI

Abstract

Threshold voltage VT of a transistor degrades with time both due to the formation of defects at the oxide/Si interface, as well as charge trapping into bulk defects - a phenomenon commonly known as Bias Temperature Instability (BTI). However, we have shown earlier that with appropriate mobility vs. vertical effective electric field characteristics, transistor's drivability (i.e., drain current) can be made far less sensitive to the NBTI-induced threshold voltage degradation ΔV T , than previously presumed. Higher steepness of the mobility-field characteristics results in an increase in mobility due to interface defects, which can self-compensate the effect of ΔV T on drain current. In this paper, for the first time we analyze the additional effect of PBTI-induced ΔV T in NMOS transistor parameters and show that mobility at constant gate voltage always increases with PBTI, irrespective of the mobility-field steepness. Therefore, self-compensation for PBTI is even more pronounced compared to NBTI. Next, we demonstrate the consequence of self-compensation via an intuitive analysis in simple digital circuits and show that lifetime of digital ICs increases dramatically once we incorporate the effect of self-compensation by using appropriate sign for mobility variation at constant gate voltage. This might in turn reduce the requirement of different circuit level optimization techniques, currently employed to manage transistor variabilities. Finally, we establish the importance of flatter transfer characteristics for self-compensation, which can be obtained through advanced CMOS technologies.