INVITED: Reducing Time and Effort in IC Implementation: A Roadmap of Challenges and Solutions

A. Kahng
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引用次数: 1

Abstract

To reduce time and effort in IC implementation, fundamental challenges must be solved. First, the need for (expensive) humans must be removed wherever possible. Humans are skilled at predicting downstream flow failures, evaluating key early decisions such as RTL floorplanning, and deciding tool/flow options to apply to a given design. Achieving human-quality prediction, evaluation and decision-making will require new machine learning-centric models of both tools and designs. Second, to reduce design schedule, focus must return to the long-held dream of single-pass design. Future design tools and flows that never require iteration (i.e., that never fail, but without undue conservatism) demand new paradigms and core algorithms for parallel, cloud-based design automation. Third, learning-based models of tools and flows must continually improve with additional design experiences. Therefore, the EDA and design ecosystem must develop new infrastructure for ML model development and sharing.
邀请:减少集成电路实施的时间和精力:挑战和解决方案的路线图
为了减少集成电路实施的时间和精力,必须解决一些根本性的挑战。首先,必须尽可能减少对(昂贵的)人力的需求。人类擅长预测下游流程故障,评估关键的早期决策,如RTL平面图,以及决定适用于给定设计的工具/流程选项。实现人类质量的预测、评估和决策将需要新的以机器学习为中心的工具和设计模型。其次,为了减少设计进度,重点必须回到长期以来的单次设计梦想。未来的设计工具和流程不需要迭代(即,永远不会失败,但没有过度的保守),需要新的范例和核心算法来并行,基于云的设计自动化。第三,基于学习的工具和流程模型必须通过额外的设计经验不断改进。因此,EDA和设计生态系统必须为ML模型的开发和共享开发新的基础设施。
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