Digital Read-Out Modules of CRYO System-an-Chip ASIC for Cryogenic TPC Detectors

Abstract

This work describes the primary modules of the digital read-out system implemented in a System-On-Chip (SoC) ASIC optimized for noble liquid Time Projection Chambers (TPCs). The ASIC, referred here as CRYO, performs digital and analog functions and has been designed as the charge read-out system for neutrino science experiments. The digital back-end of the chip provides data throughput up to 1 Gbps and operates with cryogenic liquids (Liquid Xenon, 160 K and Liquid Argon, 87 K). The ASIC is fabricated with 130 nm CMOS technology and the read-out process implements a sequential digital multiplexer, a custom encoder, a high-speed serializer, and LVDS (Low-Voltage Differential Signaling) drivers assisted with pre-emphasis techniques to preserve signal integrity up to 25 m cable length. The back-end system is fully programmable through a dedicated slow control unit interface to operate across temperatures and different cable lengths. A subset of simulation results of the readout of CRYO at target temperatures are validated using a custom verification flow.