A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range

A. Quelen, G. Pillonnet, P. Flatresse, E. Beigné
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引用次数: 15

Abstract

Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations, but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators, such as switched capacitor converters that need to be controlled accurately. Also, for fine-grained compensation, level shifters are required, impacting circuit performance. As FDSOI technology offers the ability to adjust transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting on buried Nwell (NW) and Pwell (PW) voltages, back-biasing generators have been investigated [3-5]. However, they require an external controller to reach the optimal Back Bias (BB) voltages (no self-adjustment) ([3-4] and [5]), imposing a non-negligible area overhead for a sub-mm2 digital core having a narrow compensation range limited to 0.35–0.45V VDD. We therefore propose a variation-aware BB compensation unit (BBC), which dynamically self-adjusts the N- and PMOS transistors' BB voltages to maintain the target frequency with low-latency tuning (100μs) across a wide range of supply voltage (0.35–1V) and temperature (−40–125°C). The low reported area of 0.0067mm2 makes it affordable for a small digital core area (0.1–2mm2). Requiring only a reference frequency signal FTGT, the self-operating BBC exhibits 2.5μW quiescent current without any external components. Compared to a worst-case design strategy, the BBC unit brings up to 50% leakage reduction @0.45VDD, 120°C and reduces the energy per cycle up to 32% compared to worst-case design. By providing continuous BB voltage adjustment (continuous VTH tuning), the target frequency is maintained within ±3.5% accuracy.
2.5μW 0.0067mm2自动反偏补偿单元,在0.35- 1v VDD范围内,FDSOI 28nm漏损降低50%
最坏情况设计和后硅调谐是成熟的数字设计实践,可以减少存在工艺、温度、老化和电压变化时的时序违规,但它们由于过度设计而遭受额外的功耗[1]。自适应电压缩放(AVS)[2]和体偏置调制[1]是众所周知的策略,可以动态确保数字核心可以在目标频率下工作,即使存在由于变化而导致的延迟退化。在多电压岛环境中,AVS需要许多集成电源发电机,例如需要精确控制的开关电容转换器。此外,对于细粒度补偿,电平移位器是必需的,影响电路性能。由于FDSOI技术能够通过作用于埋地Nwell (NW)和Pwell (PW)电压,通过高灵敏度(85mV/VBB) VTH调谐来调节晶体管速度,因此人们研究了反偏置发电机[3-5]。然而,它们需要一个外部控制器来达到最佳的反向偏置(BB)电压(没有自我调节)([3-4]和[5]),这对补偿范围限制在0.35-0.45V VDD的亚mm2数字核心施加了不可忽略的面积负载。因此,我们提出了一种变化感知BB补偿单元(BBC),它可以动态自调整N-和PMOS晶体管的BB电压,在宽电压范围(0.35-1V)和温度范围(- 40-125°C)内以低延迟调谐(100μs)保持目标频率。0.0067mm2的低报告面积使其能够承受较小的数字核心区域(0.1-2mm2)。仅需要参考频率信号FTGT,无需任何外部元件,自工作BBC的静态电流为2.5μW。与最坏情况设计策略相比,BBC单元在120°C的情况下可减少50%的泄漏,并且与最坏情况设计相比,每循环减少32%的能量。通过提供连续的BB电压调节(连续VTH调谐),目标频率保持在±3.5%的精度内。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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